The present disclosure relates generally to integrated circuits, such as field-programmable gate arrays (FPGAs). More particularly, the present disclosure relates to adder circuitry to perform large arithmetic operations implemented using circuitry elements of an integrated circuit (e.g., programmable logic of an FPGA).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits increasingly carry out functions, such as encryption, that have become essential to everyday life. Indeed, encryption is becoming increasingly valuable in a number of technical fields, such as financial transaction security. Encryption (as well as many other operations that may take place on an integrated circuitry, such as certain multiplication operations) may use increasingly large precision arithmetic that, in some cases, may involve a final addition operation to sum operands having a large precision. In some cases, for example, the precision of the operands may be on the order of thousands of bits. The final addition operation may be carried out by a final adder circuit. However, since the final adder circuit may include smaller adder circuits chained together to accommodate the large precision arithmetic involved with summing the operands, the final adder circuit may represent a critical path for an encryption and/or multiplication operation implemented on an integrated circuit. In fact, the final adder may consume a relatively large area of the integrated circuit, consume a relatively large amount of power, and/or produce additional latency in the integrated circuit.